TLD5095EL_15 Datasheet, PDF (9/35 Pages) Infineon Technologies AG – Multitopology LITIX Power DC/DC Controller IC

Infineon® LITIX™ Power
TLD5095EL
General Product Characteristics
4.2
Functional Range
Table 4-2 Functional Range
Parameter
Symbol
Min.
Supply Voltage
Feedback Voltage
Input
V_IN
V_FBH; V_FBL
4.75
4.5
Junction
T_j
-40
Temperature
Values
Typ. Max.
45
45
150
Unit
V
V
Note or
Test Condition
V_IVCC > V_IVCC,RTH,d
Number
P_4.2.1
P_4.2.2
°C
P_4.2.3
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Table 4-3 Thermal Resistance
Parameter
Symbol
Values
Unit Note or
Number
Min.
Typ. Max.
Test Condition
Junction to Case¹⁾²⁾ R_thJC
10
Junction to Ambient³⁾ R_thJA
42
Junction to Ambient R_thJA
42
Junction to Ambient R_thJA
42
1) Not subject to production test, specified by design.
K/W
K/W 2s2p
K/W 1s0p + 600mm²
K/W 1s0p + 300mm²
P_4.3.1
P_4.3.2
P_4.3.3
P_4.3.4
2) Specified R_thJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed to
ambient temperature). Ta=25°C is dissipating 1W.
3) Specified R_thJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink
area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5mm board. The 2s2p board
has 2 outer copper layers (2 x 70µm Cu) and 2 inner copper layers (2 x 35µm Cu), A thermal via (diameter = 0.3mm and
25µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and
second outer layer (bottom) of the JEDEC PCB. Ta=25°C, IC is dissipating 1W
Data Sheet
9
Revision 1.4
2015-03-11