TLD1326EL_15 Datasheet, PDF (9/34 Pages) Infineon Technologies AG – 3 Channel High Side Current Source

TLD1326EL
General Product Characteristics
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos. Parameter
4.2.20
4.2.21
Supply voltage range for
normal operation
Power on reset threshold
4.2.22 Junction temperature
Symbol
V_S(nom)
Limit Values
Min.
Max.
5.5
40
V_S(POR) –
5
T_j
-40
150
Unit Conditions
V
–
V
V_EN = V_S
R_SET = 12 kΩ
I_OUTx = 80% I_OUTx(nom)
V_OUTx = 2.5 V
°C –
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Case
R_thJC
–
4.3.2 Junction to Ambient 1s0p board R_thJA1
–
–
4.3.3 Junction to Ambient 2s2p board R_thJA2
–
–
8
10
K/W ^{1) 2)}
K/W ^{1) 3)}
61
–
56
–
K/W
T_a = 85 °C
T_a = 135 °C
1) 4)
45
–
43
–
T_a = 85 °C
T_a = 135 °C
1) Not subject to production test, specified by design. Based on simulation results.
2) Specified R_thJC value is simulated at natural convection on a cold plate setup (all pins and the exposed Pad are fixed to
ambient temperature). T_a = 85°C, Total power dissipation 1.5 W.
3) The R_thJA values are according to Jedec JESD51-3 at natural convection on 1s0p FR4 board. The product (chip + package)
was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 70µm Cu, 300 mm² cooling area. Total power dissipation 1.5 W
distributed statically and homogenously over all power stages.
4) The R_thJA values are according to Jedec JESD51-5,-7 at natural convection on 2s2p FR4 board. The product (chip +
package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (outside 2 x 70 µm Cu, inner 2 x
35µm Cu). Where applicable, a thermal via array under the exposed pad contacted the first inner copper layer. Total power
dissipation 1.5 W distributed statically and homogenously over all power stages.
Data Sheet
9
Rev. 1.1, 2015-03-24