PTFA091201EF Datasheet, PDF (9/10 Pages) Infineon Technologies AG – Thermally-Enhanced High Power RF LDMOS FETs

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Package Outline Specifications (cont.)
Package H-37248-2
4.83±0.51
[.190±.020]
( 45° X 2.72
[.107])
CL
D
PTFA091201E
PTFA091201F
LID 9.40^{+–00..1105}
FLANGE 9.78 ^{[.370+–..000046]}
[.385]
19.43±0.51
CL ^{[.765±.020]}
4X[ _RR.002.50+0_–.8_{0.01+0–5050]}^..318217
SPH 1.57
[.062]
G
2X 12.70
[.500]
19.81±0.20
[.780±.008]
CL
1.02
[.040]
0.0381 [.0015] -A-
0 7 1 1 1 7 _ h -3 7 2 4 8 -2 _ p o
3.61±0.38
[.142±.015]
S
20.57
[.810]
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
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Data Sheet
9 of 10
Rev. 03.1, 2016-06-21