ICE2QR0665_10 Datasheet, PDF (9/21 Pages) Infineon Technologies AG – Off-Line SMPS Quasi-Resonant PWM Controller

CoolSET^® - Q1
ICE2QR0665
Functional Description
thedetected zero-crossing to the switch-on of the main
switch t_delay, theoretically:
∆t
=
T----o----s---c-
4
–
td
e
l
ay
[2]
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
τ_td
=
Cz
c
⋅
-R-----z---c---1----^â‹---R-----z---c---2--
Rzc1 + Rzc2
[3]
To avoid mistriggering caused by the voltage spike
across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, t_LEB, is
applied to the output of the comparator. In other words,
once the gate drive is turned on, the minimum on time
of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, t_OnMax,
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
3.3.1.3 Ringing suppression time
After MOSFET is turned off, there will be some
oscillation on V_DS, which will also appear on the voltage
on ZC pin. To avoid that the MOSFET is turned on
mistriggerred by such oscillations, a ringing
suppression timer is implemented. The time is
dependent on the voltage v_ZC. When the voltage v_ZC is
lower than the threshold V_ZCRS, a longer preset time
applies, while a shorter time is set when the voltage v_ZC
is higher than the threshold.
3.3.1.4 Switch on determination
After the gate drive goes to low, it can not be changed to high
during ring suppression time.
After ring suppression time, the gate drive can be turned on
when the ZC counter value is higher or equal to up/down
counter value.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps very fast
and IC can not detect enough zero crossings and ZC counter
value will not be high enough to turn on the gate drive. In this
case, a maximum off time is implemented. After gate drive
has been remained off for the period of T_OffMax, the gate drive
will be turned on again regardless of the counter values and
V_ZC. This function can effectively prevent the switching
frequency from going lower than 20kHz, otherwise which
will cause audible noise, during start up.
3.3.2
Switch Off Determination
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor v_CS is applied to an internal current
measurement unit, and its output voltage V₁ is
compared with the regulation voltage V_FB. Once the
voltage V₁ exceeds the voltage V_FB, the output flip-flop
is reset. As a result, the main power switch is switched
off. The relationship between the V₁ and the v_CS is
described by:
V1 = 3.3 ⋅ Vcs + 0.7
[4]
3.4
Current Limitation
There is a cycle by cycle current limitation realized by the
current limit comparator to provide an overcurrent detection.
The source current of the MOSFET is sensed via a sense
resistor R_CS. By means of R_CS the source current is
transformed to a sense voltage V_CS which is fed into the pin
CS. If the voltage V_CS exceeds an internal voltage limit,
adjusted according to the Mains voltage, the comparator
immediately turns off the gate drive.
To prevent the Current Limitation process from distortions
caused by leading edge spikes, a Leading Edge Blanking
time (t_LEB) is integrated in the current sensing path.
A further comparator is implemented to detect dangerous
current levels (V_CSSW) which could occur if one or more
transformer windings are shorted or if the secondary diode is
shorted. To avoid an accidental latch off, a spike blanking
time of t_CSSW is integrated in the output path of the
comparator .
3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on time
becomes shorter and therefore the operating frequency is
also increased. As a result, for a constant primary current
limit, the maximum possible output power is increased,
which the converter may have not been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the V_CS voltage limit according to
the bus voltage. This means the V_CS will be decreased when
the bus voltage increases. To keep a constant maximum
input power of the converter, the required maximum V_CS
Version 2.3
9
April 27, 2010