XC858CA Datasheet, PDF (81/124 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

Count
FFFF_H
WDTWINB
WDTREL
XC858CA
Functional Description
time
No refresh
allowed
Refresh allowed
Figure 25 WDT Timing Diagram
Table 23 lists the possible watchdog time ranges that can be achieved using a certain
module clock. Some numbers are rounded to 3 significant digits.
Table 23 Watchdog Time Ranges
Reload value
In WDTREL
Prescaler for f_PCLK
2 (WDTIN = 0)
24 MHz
FF_H
21.3 µs
7F_H
2.75 ms
00_H
5.46 ms
128 (WDTIN = 1)
24 MHz
1.37 ms
176 ms
350 ms
3.11
UART and UART1
The XC858 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– Fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
Data Sheet
74
V1.0, 2010-03