XC858CA Datasheet, PDF (113/124 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

XC858CA
Electrical Parameters
4.3.3 Power-on Reset and PLL Timing
Table 40 provides the characteristics of the power-on reset and PLL timing in the
XC858.
Table 40 Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min. typ. max.
On-Chip Oscillator
start-up time
t_OSCST
CC –
–
500 ns ¹⁾
PLL lock-in in time
t_LOCK
CC –
–
200 µs ¹⁾
PLL accumulated jitter D_P
–
–
1.8 ns ¹⁾²⁾
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) PLL lock at 144 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 72 and P = 1.
VDDP
VDDC
V_PAD
OSC
t_OSCST
PLL
PLL unlock
PLL lock
t_LOCK
Pads
2)P ull/ I nput
1)
Pad state undefined
3)As Programmed
I)until EVR is stable II)until PLL is locked ^{III) Reset is released}
and start of program
Figure 38 Power-on Reset Timing
Data Sheet
106
V1.0, 2010-03