TLE7230R Datasheet, PDF (8/16 Pages) Infineon Technologies AG – Smart Octal Low-Side Switch

Target Datasheet TLE7230 R/G
Latching: After overtemperature shutdown the channel stays off until the overtemperature latch is re-
set by a new LÆH transition of the input signal.
Note: The overtemperature sensors of the output channels are only active if the channel is turned on.
Low Quiescent current mode (Sleep mode) :
By applying ay low signal at the Reset Pin the device can be set to Sleep mode. In this mode all out-
puts are turned off, the diagnosis and biasing is disabled, the diagnosis and the on/off register are re-
seted and the current consumption drastically reduced (<10µA). After a reset the outputs are Off, ex-
cept the outputs are controlled by parallel inputs.
Overload Protection:
The IC can be programmed to react in different ways to overload.
Only Current limit: The IC actively limits the current to the specified current lmit value. If the current
limitation is active for longer than the fault filtering time this fault is reported and stored in the Fault reg-
ister. The channel is not shutdown.
Current limit + shutdown: The IC actively limits the current to the specified current lmit value. If this cur-
rent limit is active for more than the specified Overload switch off delay time the affected channel is
turned off and the fault is reported and stored in the fault register. To turn on the channel again this
overload latch has to be reset before with an LÆ H transition of the input signal (parallel /SPI depend-
ing on the programmed operation).
Pin description:
OUTPUT 1 to 8 – Drain pins of the 8 channels. Output pins and connected to the load.
GND – Ground pins.
IN 1 to 3 – Parallel Input Pins of the channels 1 to 3
IN 4 / IN – Mappable parallel Input Pin. Can be assigned to different outputs by SPI command. Default
Output is OUT4
PRG - Program pin. PRG = High (V_S): Parallel inputs 1 to 4 are high active
PRG = Low (GND): Parallel inputs 1 to 4 are low active.
If the parallel input pins are not connected (independent of high or low activity) it is guaranteed
that the channels 1 to 4 are switched OFF.
PRG pin itself is internally pulled up when it is not connected.
Reset - If the reset pin is in a logic low state, it clears the SPI shift register and switches all
outputs OFF. An internal pull-up structure is provided on chip.
Fault - There is a general fault pin (open drain) which shows a high to low transition as soon
as an error occurs for any one of the eight channels. This fault indication can be used to gen-
erate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault
indication. This saves processor time compared to a cyclic reading of the SO information.
VDO – Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state
output voltage of the SO pin.
Vs – Logic supply pin. This pin is used to supply the integrated circuitry.
CS – Chip Select of the SPI
V1.1
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12. Oct. 2003