TLE6711_07 Datasheet, PDF (8/25 Pages) Infineon Technologies AG – Multifunctional Voltage Regulator and Watchdog

TLE 6711
Circuit Description
4
Circuit Description
Below some important sections of the TLE 6711 G/GL are described in more detail.
4.1
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed. In case of V_CC power
down (V_CC < V_RT for t > t_RR) a logic LOW signal is generated at the pin RO to reset an external microcontroller.
When the level of V_CC reaches the reset threshold V_RT, the signal at RO remains LOW for the Power-up reset delay
time t_RD before switching to HIGH. If V_CC drops below the reset threshold V_RT for a time extending the reset
reaction time t_RR, the reset circuit is activated and a power down sequence of period t_RD is initiated. The reset
reaction time t_RR avoids wrong triggering caused by short “glitches” on the V_CC-line.
V_CC
< t_RR
< t_RD
typ. 4.65 V
V_RT
1V
Start-Up ON Delay
RO
H
Invalid
L
Power Start-Up
t_RD
Normal
Figure 4 Reset Function
ON Delay
Started
ON Delay
Stopped
Invalid
t_RR
Failed
Invalid
N Failed
t
t_RD
t
Normal
AET02950
4.2
Watchdog Operation
The watchdog uses one hundred of the oscillator’s clock signal period as a timebase, defined as the watchdog
cycle time t_CYL.
After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time
t_RD, i.e. 64 cycles. With the LOW to HIGH transition of the signal at RO the device starts the closed window time
t_CW = 32 cycles. A trigger signal within this window is interpreted as a pretrigger failure according to the figures
shown below. After the closed window the open window with the duration t_OW is started. The open window lasts
at minimum until the trigger process has occurred, at maximum t_OW is 32 cycles.
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken by a trigger. To avoid wrong triggering
due to parasitic glitches two HIGH samples followed by two LOW samples (sample period t_CYL) are decoded as a
valid trigger. If a trigger signal appears at the watchdog input pin WDI during the open window or a power up/down
occurs, the watchdog window signal is reset and a new closed window follows.
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. This reset happens after 64 cycles after the latest valid closed window start time and
lasts for further 64 cycles.
The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are
inside the closed window and only the fourth sample (the second LOW sample) is taken in the open window.
In addition to the microcontroller reset signal RO the device generates a system enable signal at pin SEN. If RO
Data Sheet
8
Rev. 3.4, 2007-08-16