SLE66CX640P Datasheet, PDF (8/9 Pages) Infineon Technologies AG – Security & Chip Card ICs

SLE 66CX640P
General Description
SLE 66CX640P is another member of Infineon Technologies high end security controller family in
advanced 0.25 µm CMOS technology. The CPU provides the high efficiency of the SAB 8051
instruction set extended by additional powerful instructions together with enhanced performance,
memory sizes and security features. The internal clock frequency can be adjusted up to 15 MHz
independent of the clock rate of the terminal with the help of the PLL.
The controller IC offers 135 Kbytes of User-ROM, 256 byte internal RAM, 4096 byte XRAM and
64 Kbytes EEPROM. The Memory Management and Protection Unit allows a secure separation of
the operating system and the applications. Furthermore the MMU makes a secure downloading of
applications possible after the personalization of a card. These new features suit the requirements
of the next generation of multi application operating systems. For code compatibility to the SLE
66CxxS family, a transparent mode for the MMU is established which allows to keep the memory
mapping of the SLE 66CxxS products.
Voltage
Clock
Reset
ROM
XRAM EEPROM DES-EC2
Advanced
136 Kbyte 4 Kbyte 64 Kbyte Accelerator Crypto Engine
16-Bit CPU with
MMU
&
ECO 2000
Instruction Set
Sleep Mode Logic
Sensors/Filters
Voltage Regulator
Interrupt
Address-/Data Bus
two
16-bit
Timer
CRC
Random
Number
Generator
UART
PLL
Figure 2: Block Diagram SLE 66CX640P
The CRC module allows the easy generation of checksums according to ISO/IEC 3309 (16-Bit-
CRC). To minimize the overall power consumption, the chip card controller IC offers a sleep mode.
The UART supports the half-duplex transmission protocols T=0 and T=1 according to ISO/IEC
7816-3. All relevant transmission parameters can be adjusted by software, as e.g. the clock
division factor, direct/inverse convention and the number of stop bits. Additionally, the I/O port can
be driven by communication routines realized in software.
The Advanced Crypto Engine is equipped with its own RAM of 700 bytes and supports all of today
known public-key algorithms based on large integer modular arithmetic. It allows fast and efficient
calculation of e.g. RSA operations with key lengths up to 2048 bit.
The DDES-EC2 accelerator consists of two modules. The DES module supports symmetrical
crypto algorithms according to the Data Encryption Standard in the Electronic Code Book Mode.
The EC2 module accelerates the multiplication in GF(2ⁿ) and therefore the operations for elliptic
curve cryptography.
The random number generator (RNG) is able to supply the CPU with true random numbers on all
conditions.
As an important feature, the chip provides a new and enhanced level of on-chip security.
Short Product Information
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