TLE7274-2 Datasheet, PDF (7/19 Pages) Infineon Technologies AG – 5-V Low Dropout Voltage Regulator

TLE7274-2
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
TLE7274-2E (PG-SSOP-14 Exposed Pad)
4.3.1 Junction to Case¹⁾
R_thJC
–
14
–
K/W measured to
exposed pad
4.3.2
4.3.3
4.3.4
Junction to Ambient¹⁾
R_thJA
–
R_thJA
–
R_thJA
–
47
–
141 –
66
–
K/W
K/W
K/W
2)
footprint only³⁾
300 mm² heatsink
area³⁾
4.3.5
R_thJA
–
56
–
K/W 600 mm² heatsink
area³⁾
TLE7274-2D (PG-TO252-3)
4.3.1
4.3.2
4.3.3
4.3.4
Junction to Case¹⁾
Junction to Ambient¹⁾
R_thJC
–
R_thJA
–
R_thJA
–
R_thJA
–
6
–
32
–
115 –
62
–
K/W measured to tab
K/W ²⁾
K/W footprint only³⁾
K/W 300 mm² heatsink
area³⁾
4.3.5
R_thJA
–
47
–
K/W 600 mm² heatsink
area³⁾
TLE7274-2G (PG-TO263-3)
4.3.1 Junction to Case¹⁾
R_thJC
–
6
–
K/W measured to
exposed pad
4.3.2
4.3.3
4.3.4
Junction to Ambient¹⁾
R_thJA
–
R_thJA
–
R_thJA
–
27
–
75
–
47
–
K/W ²⁾
K/W footprint only³⁾
K/W 300 mm² heatsink
area³⁾
4.3.5
R_thJA
–
38
–
K/W 600 mm² heatsink
area³⁾
1) Not subject to production test, specified by design.
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
7
Rev. 1.01, 2011-11-30