TLE7230R_05 Datasheet, PDF (7/14 Pages) Infineon Technologies AG – Smart Octal Low-Side Switch Low Quiescent Current< 10μA Overvoltage

Data Sheet TLE 7230R
Note: The overtemperature sensors of the output channels are only active if the channel is turned on.
Low Quiescent Current Mode (Sleep Mode) :
By applying a low signal at the Reset Pin, the device can be set to sleep mode. In this mode, all outputs
are turned off, diagnosis and biasing are disabled, the diagnosis and the on/off register are reset and the
current consumption is drastically reduced (<10µA). Once the reset signal returns to high, all outputs
except for those controlled by parallel inputs remain off.
Overload Protection:
The IC can be programmed to react in different ways to overload.
• Only Current limit: The IC actively limits the current to the specified current limit value. If the
current limitation is active for longer than the fault filtering time, a fault is reported and stored in
the Fault register. Unless the channel reaches the overtemperature shutdown threshold, the
channel is not shutdown.
• Current limit + shutdown: The IC actively limits the current to the specified current limit value.
If this current limit is active for more than the specified Overload switch off delay time the af-
fected channel is turned off and the fault is reported and stored in the fault register. To turn on
the channel again this overload latch must be reset with a Là H transition of the input signal
(parallel /SPI depending on the programmed operation).
Pin description:
OUTPUT 1 to 8 – Drain pins of the 8 channels. Output pins to connect to loads.
GND – Ground pins.
IN 1 to 3 – Parallel Input Pins of the channels 1 to 3
IN 4 – Mapable parallel Input Pin. Can be assigned to different outputs by SPI command. Default Output
is OUT4
PRG - Program pin. PRG = High (V_S): Parallel inputs 1 to 4 are high active
PRG = Low (GND): Parallel inputs 1 to 4 are low active.
If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that
the channels 1 to 4 are switched OFF.
PRG pin itself is internally pulled up when not connected.
Reset - If the reset pin is in a logic low state, it clears the SPI shift register and switches all out-
puts OFF. An internal pull-up structure is provided on chip.
Fault - There is a general fault pin (open drain) which shows a high to low transition as soon as an
error occurs at any one of the eight channels. This fault indication can be used to generate a µC
interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication.
This saves processor time compared to a cyclic reading of the SO information.
VDO – Supply pin of the Signal Output (SO) pin of the SPI interface . This pin can be used to vary the
high-state output voltage of the SO pin.
Vs – Logic supply pin. This pin is used to supply the integrated circuitry.
V2.0
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2005-10-05