ICE2QR1765Z Datasheet, PDF (7/22 Pages) Infineon Technologies AG – Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V CoolMOS® and startup cell in DIP-7

CoolSET^® - Q1
ICE2QR1765Z
Functional Description
3 Functional Description
3.1 VCC Pre-Charging and Typical
VCC Voltage During Start-up
In ICE2QR1765Z, a startup cell is integrated into the
CoolMOS^®. As shown in Figure 2, the start cell consists
of a high voltage device and a controller, whereby the
high voltage device is controlled by the controller. The
startup cell provides a pre-charging of the VCC
capacitor till VCC voltage reaches the VCC turned-on
threshold V_VCCon and the IC begins to operate.
Once the mains input voltage is applied, a rectified
voltage shows across the capacitor C_bus. The high
voltage device provides a current to charge the VCC
capacitor C_vcc. Before the VCC voltage reaches a
certain value, the amplitude of the current through the
high voltage device is only determined by its channel
resistance and can be as high as several mA. After the
VCC voltage is high enough, the controller controls the
high voltage device so that a constant current around
1mA is provided to charge the VCC capacitor further,
until the VCC voltage exceeds the turned-on threshold
V_VCCon. As shown in the time phase I in Figure 3, the
VCC voltage increase near linearly and the charging
speed is independent of the mains voltage level.
3.2
Soft-start
As shown in Figure 4, at the time t_on, the IC begins to
operate with a soft-start. By this soft-start the switching
stresses for the switch, diode and transformer are
minimised. The soft-start implemented in
ICE2QR1765Z is a digital time-based function. The
preset soft-start time is 12ms with 4 steps. If not limited
by other functions, the peak voltage on CS pin will
increase step by step from 0.32V to 1V finally.
Vcs_sst
(V)
1.00
0.83
0.66
0.49
0.32
ton
3
6
9
12 _Time(ms)
Figure 4
Maximum current sense voltage during
softstart
V_VCC
V_VCCon
V_VCCoff
I
II
III
t1 t2
t
Figure 3 VCC voltage at start up
The time taking for the VCC pre-charging can then be
approximately calculated as:
t1
=
V-----V-----C----C-----o---n-----×_{---C----v---c----c-}
IVCCch _arge2
[1]
3.3
Normal Operation
The PWM controller during normal operation consists
of a digital signal processing circuit including an up/
down counter, a zero-crossing counter (ZC counter)
and a comparator, and an analog circuit including a
current measurement unit and a comparator. The
switch-on and -off time points are determined by the
digital circuit and the analog circuit respectively. The
zero-crossing input signal and the value of the up/down
counter are needed for the switch-on determination
while the feedback signal V_FB and the current sensing
signal V_CS are necessary for the switch-off
determination. Details about the full operation of the
PWM controller in normal operation are illustrated in
the following paragraphs.
where I_VCCcharge2 is the charging current from the
startup cell which is 1.05mA, typically.
When the VCC voltage exceeds the VCC turned-on
threshold V_VCCon at time t₁, the startup cell is switched
off and the IC begins to operate with soft-start. Due to
power consumption of the IC and the fact that there is
still no energy from the auxiliary winding to charge the
VCC capacitor before the output voltage is built up, the
VCC voltage drops (Phase II). Once the output voltage
is high enough, the VCC capacitor receives the energy
from the auxiliary winding from the time point t₂ onward.
The VCC will then reach a constant value depending
on output load.
3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing
circuit consists of an up/down counter, a ZC counter
and a comparator. These three parts are key to
implement digital frequency reduction with decreasing
load. In addition, a ringing suppression time controller
is implemented to avoid mistriggering by the high
frequency oscillation when the output voltage is very
low under conditions such as soft start period or output
short circuit. Functionality of these parts is described in
the following.
Version 2.1
7
August 30, 2011