C161CS-32R Datasheet, PDF (61/89 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C161CS/JC/JI-32R
C161CS/JC/JI-L
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 10 associates the combinations of these three bits with the respective clock
generation mode.
Table 10 C161CS/JC/JI Clock Generation Modes
CLKCFG CPU Frequency External Clock
(P0H.7-5) f_CPU = f_OSC × F Input Range¹⁾
Notes
1 1 1 f_OSC × 4
2.5 to 6.25 MHz Default configuration
1 1 0 f_OSC × 3
3.33 to 8.33 MHz –
1 0 1 f_OSC × 2
5 to 12.5 MHz
–
100
011
f_OSC × 5
f_OSC × 1
2 to 5 MHz
1 to 25 MHz
–
Direct drive²⁾
0 1 0 f_OSC × 1.5
6.66 to 16.6 MHz –
0 0 1 f_OSC / 2
2 to 50 MHz
CPU clock via prescaler
0 0 0 f_OSC × 2.5
4 to 10 MHz
–
1) _{The external clock input range refers to a CPU clock range of 10 … 25 MHz.}
2) _{The maximum frequency depends on the duty cycle of the external clock signal.}
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001_B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f_CPU is half the frequency of f_OSC and the high and low time of f_CPU
(i.e. the duration of an individual TCL) is defined by the period of the input clock f_OSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of f_OSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f_CPU = f_OSC × F). With every F’th transition of f_OSC the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f_CPU is constantly adjusted so
it is locked to f_OSC. The slight variation causes a jitter of f_CPU which also effects the
duration of individual TCLs.
Data Sheet
57
V3.0, 2001-01