V23833-G2005-A101 Datasheet, PDF (6/27 Pages) Infineon Technologies AG – XPAK 850 nm Module 10 Gigabit Pluggable Transceiver Compatible with XPAK MSA Rev. 2.3

Pin Description (cont’d)
Signal Name Level
I/O
Transmit Functions
Reserved
I
Reserved
I
TX LANE 3–
TX LANE 3+
TX LANE 2–
TX LANE 2+
TX LANE 1–
TX LANE 1+
AC-coupled, I
Internally I
biased
I
differential _I
XAUI
I
I
TX LANE 0–
I
TX LANE 0+
I
Receive Functions
Reserved
O
Reserved
O
RX LANE 0+ AC-coupled, O
RX LANE 0– Internally O
RX LANE 1+ ^biased
O
RX LANE 1– ^differential O
RX LANE 2+ ^XAUI
O
RX LANE 2–
O
RX LANE 3+
O
RX LANE 3–
O
Pin No.
68
67
65
64
62
61
59
58
56
55
38
39
41
42
44
45
47
48
50
51
V23833-Gx005-A1x1
Pin Configuration
Description
Reserved For Future Use
Reserved For Future Use
Module XAUI Input Lane 3–
Module XAUI Input Lane 3+
Module XAUI Input Lane 2–
Module XAUI Input Lane 2+
Module XAUI Input Lane 1–
Module XAUI Input Lane 1+
Module XAUI Input Lane 0–
Module XAUI Input Lane 0+
Reserved For Future Use
Reserved For Future Use
Module XAUI Output Lane 0+
Module XAUI Output Lane 0–
Module XAUI Output Lane 1+
Module XAUI Output Lane 1–
Module XAUI Output Lane 2+
Module XAUI Output Lane 2–
Module XAUI Output Lane 3+
Module XAUI Output Lane 3–
Preliminary Product Information
6
2004-05-13