TLE6208-6G_07 Datasheet, PDF (6/25 Pages) Infineon Technologies AG – Hex-Half-Bridge / Double Six-Driver

TLE 6208-6 G
1.5 Circuit Description
Figure 2 shows a block schematic diagram of the module.
There are 6 halfbridge drivers on the right-hand side. An HS driver and an LS driver are
combined to form a halfbridge driver in each case.
The drivers communicate via the internal data bus with the logic and the other control
and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD),
charge pump and fault detect.
Two connection interfaces are provided for supply to the module: All power drivers are
connected to the supply voltage V_S. These are monitored by overvoltage and
undervoltage comparators with hysteresis, so that the correct function can be checked
in the application at any time.
The logic is supplied by the V_CC voltage, typ. with 5 V. The V_CC voltage uses an internally
generated Power-On Reset (POR) to initialize the module at power-on. The advantage
of this system is that information stored in the logic remains intact in the event of short-
term failures in the supply voltage V_S. The system can therefore continue to operate
following V_S undervoltage, without having to be reprogrammed. The “undervoltage”
information is stored, and can be read out via the interface. The same logically applies
for overvoltage. “Interference spikes” on V_S are therefore effectively suppressed.
The situation is different in the case of undervoltage on the V_CC connection pin. If this
occurs, then the internally stored data is deleted, and the output levels are switched to
high-impedance status (tristate). The module is initialized by V_CC following restart
(Power-On Reset = POR).
The 16-bit wide programming word or control word (see Table 1) is read in via the DI
data input, and this is synchronized with the clock input CLK. The status word appears
synchronously at the DO data output (see Table 2).
The transmission cycle begins when the chip is selected with the CSN input (H to L). If
the CSN input changes from L to H then the word which has been read in becomes the
control word. The DO output switches to tristate status at this point, thereby releasing the
DO bus circuit for other uses.
The INH inhibit input can be used to cut off the complete module. This reduces the
current consumption to just a few µA, and results in the loss of any data stored. The
output levels are switched to tristate status. The module is reinitialized with the internally
generated POR (Power-On Reset) at restart.
This feature allows the use of this module in battery-operated applications (vehicle body
control applications).
Every driver block from DRV 1 to 6 contains a low-side driver and a high-side driver. The
output connections have been selected so that each HS driver and LS driver pair can be
combined to form a halfbridge by short-circuiting adjacent connections. The full flexibility
of the configuration can be achieved by dissecting the halfbridges into “quarter-bridges”.
Table 3 shows examples of possible applications.
Data Sheet
6
2007-09-12