TLE6208-6G_07 Datasheet, PDF (17/25 Pages) Infineon Technologies AG – Hex-Half-Bridge / Double Six-Driver

TLE 6208-6 G
2.3 Electrical Characteristics (cont’d)
8 V < V_S < 40 V; 4.75 V < V_CC < 5.25 V; INH = High; all outputs open; – 40 °C < T_j < 150 °C;
unless otherwise specified
Parameter
Symbol Limit Values Unit Test Condition
min. typ. max.
Data Input Timing
Clock period
Clock high time
Clock low time
Clock low before CSN low
CSN setup time
CSN high time
CLK setup time
Clock low after CSN high
DI setup time
DI hold time
Input signal rise time
at pin DI, CLK and CSN
Input signal fall time
at pin DI, CLK and CSN
t_pCLK
t_CLKH
t_CLKL
t_bef
t_lead
t_CSNH
t_lag
t_beh
t_DISU
t_DIHO
t_rIN
t_fIN
500 –
250 –
250 –
250 –
250 –
12 –
250 –
250 –
40 –
40 –
–
–
–
–
– ns –
– ns –
– ns –
– ns –
– ns –
– µs –
– ns –
– ns –
– ns –
– ns –
200 ns –
200 ns –
Data Output Timing
DO rise time
t_rDO
– 50 100 ns C_L = 100 pF
DO fall time
t_fDO
– 50 100 ns C_L = 100 pF
DO enable time
t_ENDO
–
– 250 ns low impedance
DO disable time
t_DISDO
–
– 250 ns high impedance
DO valid time
t_VADO
–
100 250 ns V_DO < 0.2 V_CC;
V_DO > 0.7 V_CC;
C_L = 100 pF
Note: SPI timing ia guaranteed by design. CSN high time: This is the minimum time the
user must wait between SPI commands.
Data Sheet
17
2007-09-12