TLE4253 Datasheet, PDF (6/22 Pages) Infineon Technologies AG – Low Dropout Voltage Tracking Regulator

TLE4253
General Product Characteristics
4.2
Functional Range
Pos. Parameter
Symbol Limit Values Unit Conditions
Min. Max.
4.2.1
4.2.1
Input Voltage
Adjust / Enable Input Voltage
(Voltage Tracking Range)
V_I
3.5 40
V_ADJ/EN 2.0
–
V
V_I ≥ V_Q + V_dr
V
–
4.2.2 Junction Temperature
T_j
-40 150
4.2.3 Output Capacitor Requirements C_Q
10
4.2.4
ESR_CQ –
5
°C
–
µF
–¹⁾
Ω
–²⁾
1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
2) relevant ESR value at f = 10 kHz.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos. Parameter
Symbol
Limit Value
Unit Conditions
Min. Typ. Max.
PG-DSO-8:
4.3.1 Junction to Soldering Point R_thJSP –
4.3.2
4.3.3
Junction to Ambient
R_thJA
–
–
4.3.4
–
4.3.5
–
39
–
150 –
91
–
81
–
65
–
K/W Pins 2 - 3 and 6 - 7
fixed to T_A
K/W Footprint only ¹⁾
K/W 300 mm² PCB heatsink
area ¹⁾
K/W 600 mm² PCB heatsink
area ¹⁾
K/W 2s2p board²⁾
PG-DSO-8 exposed pad:
4.3.6 Junction to Case Bottom R_thJC
–
9
–
K/W Measured to exposed
bottom pad
4.3.7
4.3.8
Junction to Ambient
R_thJA
–
–
169 –
64
–
K/W Footprint only ¹⁾
K/W 300 mm² PCB heatsink
area ¹⁾
4.3.9
–
55
–
K/W 600 mm² PCB heatsink
area ¹⁾
4.3.10
–
49
–
K/W 2s2p board²⁾
1) Package mounted on PCB FR4; 80 x 80 x 1.5 mm; 35 µm Cu, 5 µm Sn; horizontal position; zero airflow.
Not subject to production test; specified by design.
2) Specified R_thJA value is according to JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package)
was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the package contacted the first inner copper layer.
Data Sheet
6
Rev. 1.2, 2009-11-09