HYR166420G-845 Datasheet, PDF (6/14 Pages) Infineon Technologies AG – Direct RDRAM RIMM Modules (with 144 Mbit RDRAMs)

HYR 16xx20G/HYR 18xx20G
Rambus RIMM Modules
Module Connector Pad Description (cont’d)
Signal
Module Connector Pads I/O
LDQB8 …
LDQB0
B32, A32, B30, A30, B28, I/O
A28, B26, A26, B24
LROW2 … B16, A18, B18
I
LROW0
LSCK
A34
I
N.C.
A16, B14, A38, B38, A40, –
B40, A77, B79;A43, B43,
A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48,
A49, B49, A50, B50
Type
RSL
RSL
V_CMOS
–
Description
Data bus B. A 9-bit bus carrying a
byte of read or write data between
the Channel and the RDRAM.
LDQB8 is non-functional on
modules with x16 RDRAM devices.
Row bus. 3-bit bus containing
control and address information for
row accesses.
Serial Clock input. Clock source
used to read from and write to the
RDRAM control registers.
These pads are not connected.
These connector pads are reserved
for future use.
RCFM
RCFMN
RCMD
RCOL4 …
RCOL0
RCTM
RCTMN
RDQA8 …
RDQA0
B83
I
B81
I
B59
I
A73, B73, A71, B71, A69 I
A79
I
A81
I
A91, B91, A89, B89, A87, I/O
B87, A85, B85, A83
RSL
RSL
V_CMOS
RSL
RSL
RSL
RSL
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock
used for receiving RSL signals from
the Channel. Negative polarity.
Serial Command Input used to read
from and write to the control
registers. Also used for power
management.
Column bus. 5-bit bus containing
control and address information for
column accesses.
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Positive polarity.
Clock to master. Interface clock
used for transmitting RSL signals to
the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a
byte of read or write data between
the Channel and the RDRAM.
RDQA8 is non-functional on
modules with x16 RDRAM devices.
INFINEON Technologies
6
7.00