TLE75080-EMD Datasheet, PDF (59/67 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control

TLE75080-EMD
10.6.2 Register structure
Serial Peripheral Interface (SPI)
The register banks the digital part have following structure:
Table 15 Register structure - all registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default
r = 0 r = 1 ADDR0
w=1 w=0
ADDR1 DATA
XXXX_H
Table 16 summarizes the available registers with their addresing space and size
Table 16 Register addressing space
Register name ADDR0 ADDR1 Size
OUT
n = 7 to 0
0000_B 00_B
n
Type
r/w
Purpose
Power output control register
bits OUT.OUTn
0_B (default) Output is OFF
1_B Output is ON
MAPIN0
n = 7 to 0
0001_B 00_B
n
r/w Input Mapping (Input Pin 0)
bits MAPIN0.OUTn
0_B (default) The output is not connected to the input pin
1_B The output is connected to the input pin
Note: Channel 2 has the corresponding bit set to “1” by
default
MAPIN1
n = 7 to 0
0001_B 01_B
n
r/w Input Mapping (Input Pin 1)
bits MAPIN1.OUTn
0_B (default) The output is not connected to the input pin
1_B The output is connected to the input pin
Note: Channel 3 has the corresponding bit set to “1” by
default
INST
0001_B 10_B
8
r
Input Status Monitor
bit TER
0_B Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1_B (default) Previous transmission failed
bits INST.RES (6:2) - reserved
bits INST.INn (1:0)
0_B (default) The input pin is set to “low”
1_B The input pin is set to “high”
First register transmitted after a reset of the logic
Data Sheet
59
Rev. 1.0, 2016-06-22