SAF-C165LMHA Datasheet, PDF (50/77 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C165
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2t_A + t_C + t_F (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol Max. CPU Clock Variable CPU Clock Unit
= 25 MHz
1 / 2TCL = 1 to 25 MHz
min. max. min.
max.
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
t₁₃ CC 50 + t_C
t₁₄ SR –
t₁₅ SR –
t₁₆ SR –
t₁₇ SR –
t₁₈ SR 0
–
3TCL - 10 –
ns
+ t_C
20 + t_C –
2TCL - 20 ns
+ t_C
40 + t_C –
3TCL - 20 ns
+ t_C
40 + t_A –
+ t_C
3TCL - 20 ns
+ t_A + t_C
50 + 2t_A –
+ t_C
4TCL - 30 ns
+ 2t_A + t_C
–
0
–
ns
Data float after RD
t₁₉ SR –
Data valid to WR
t₂₂ CC 20 + t_C
Data hold after WR
t₂₃ CC 26 + t_F
ALE rising edge after RD, t₂₅ CC 26 + t_F
WR
Address hold after RD,
WR
ALE falling edge to CS¹⁾
CS low to Valid Data In¹⁾
t₂₇ CC
t₃₈ CC
t₃₉ SR
26 + t_F
- 4 - t_A
–
CS hold after RD, WR¹⁾ t₄₀ CC 46 + t_F
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
t₄₂ CC 16 + t_A
t₄₃ CC - 4 + t_A
26 + t_F –
2TCL - 14 ns
+ t_F
–
2TCL - 20 –
ns
+ t_C
–
2TCL - 14 –
ns
+ t_F
–
2TCL - 14 –
ns
+ t_F
–
2TCL - 14 –
ns
+ t_F
10 - t_A - 4 - t_A
10 - t_A
ns
40
–
3TCL - 20 ns
+ t_C+2t_A
+ t_C + 2t_A
–
3TCL - 14 –
ns
+ t_F
–
TCL - 4 –
ns
+ t_A
–
-4
–
ns
+ t_A
Data Sheet
46
V2.0, 2000-12