SAF-C165LMHA Datasheet, PDF (19/77 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C165
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C165’s instructions can be executed
in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. All multiple-cycle instructions have been optimized so
that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit
multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
32
ROM
CPU
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr.
Instr. Reg.
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
MDH
MDL
Mul/Div-HW
Bit-Mask Gen
ALU
(16-bit)
Barrel - Shifter
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr. Code Seg. Ptr.
R15
General
Purpose
Registers
R0
Figure 5 CPU Block Diagram
16
Internal
RAM
R15
R0
16
MCB02147
Data Sheet
15
V2.0, 2000-12