TLE4473GV55-2 Datasheet, PDF (5/16 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator

TLE 4473 GV55-2
Application Information
The output voltage is divided by a voltage divider and compared to an internal reference
voltage. A regulation loop controls the Q2 output in order to achieve a stable output
voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference
voltage for the Q1 is the regulated Q2 potential (tracking regulator).
Figure 2 includes the components needed for a typical application. Maintaining the
stability of the regulation loops requires a capacitor of 10 µF both outputs. A maximum
ESR of 5 Ω is permissible for the Q2 output, while the Q1 output requires a capacitor with
a maximum ESR of 3 Ω. For both output blocking capacitors it is recommended to use
tantalum types in order to stay in the permissible ESR range over the full operating
temperature range.
At the input of the regulator a capacitor is necessary for compensating line influences. A
minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation
of long input lines of several meters an electrolytic input capacitor of 47 µF … 220 µF
should be placed at the input.
WI
RO1
RO2
Q2
N.C.
Q1
TLE 4473 GV55-2
(P-DSO-12)
1
12
2
11
3
10
4
9
5
8
6
7
GND
D2
D1
INH2
INH1
I
Figure 3 Pin Configuration (top view)
Target Data Sheet
5
Rev. 0.2, 2005-07-26