TLE4473GV55-2 Datasheet, PDF (2/16 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator

TLE 4473 GV55-2
The device features a reset with adjustable power on delay for each of the outputs. In
addition the output for the microcontroller supply comes up with a watchdog in order to
supervise a connected microcontroller
Reset and Watchdog Behavior
The reset output RO2 is in high-state if the voltage on the delay capacitor C_D2 is greater
or equal V_DU2. The delay capacitor C_D2 is charged with the current I_DC2 for output
voltages greater than the reset threshold V_RT2. If the output voltage gets lower than V_RT2
(‘reset condition’) a fast discharge of the delay capacitor C_D2 sets in and as soon as V_D2
gets lower than V_DL2 the reset output RO2 is set to low-level. The time for the delay
capacitor charge is the reset delay time. For the power-on case the charging process of
C_D2 starts from 0 V, which leads to the equation:
t_{D, on}
=
C_{-----D---2----}×_-----V_{----D---U----2}
I_DC2
(1)
for the power-on reset delay time.
When the voltage on the delay capacitor has reached V_DU2 and reset was set to high, the
watchdog circuit is enabled and discharges C_D2 with the constant current I_DD2.
If there is no rising edge observed at the watchdog input, C_D2 will be discharge down to
V_DL2. Then reset output RO2 will be set to low and C_D2 will be charged again with the
current I_DC2 until V_D2 reaches V_DU2 and reset will be set high again.
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period C_D2 is charged again and the reset output stays high. After V_D2 has reached V_DU2,
the periodical cycle starts again.
The watchdog timing is shown in Figure 1. The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time T_WI,tr. Higher
capacitances on pin D2 result in longer watchdog trigger times:
T_{WI,tr max} = 0.34 ms/nF × C_D2
(2)
If the output voltage Q1 decreases below V_RT1 (typ. 4.65 V), the external capacitor C_D1
is discharged by the reset generator of the main output. If the voltage on this capacitor
drops below V_DL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises
above the reset threshold, C_D1 will be charged with the constant current I_DC1. After the
power-on-reset time the voltage on the capacitor reaches V_DU1 and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of C_D1 using the above given equation (1) analogous for
Q1.
Target Data Sheet
2
Rev. 0.2, 2005-07-26