TLE7241E Datasheet, PDF (46/71 Pages) Infineon Technologies AG – Dual Channel Constant Current Control Solenoid Driver

TLE 7241E
Functional Description and Electrical Characteristics
5.6
SPI Command and Diagnosis Structure
5.6.1 SPI Signal Description
The SPI serial interface has the following features:
• Full duplex, 4-wire synchronous communication
• Slave mode operation only
• Fixed SCK polarity and phase requirements
• Fixed 16-bit command word
SCK operation up to 5.0 MHz (the maximum clock frequency may be limited to a value
less than 5.0 MHz by the minimum required SO setup time of the SPI master device and
by the total capacitive load on the SO bus node. With a SO load capacitance of 200 pF
the maximum SPI frequency is 3.2 MHz).
The TLE 7241E IC Serial Peripheral Interface (SPI) is used to transmit and receive data
synchronously with the master SPI device. Communication occurs over a full-duplex,
four wire SPI bus. The TLE 7241E IC will operate only as a slave device to the master,
and requires four external pins; SI, SO, SCK, and CSB. All words are 16 bits long and
sent MSB first. The device is selected when the CSB signal is asserted (low). The master
will then send 16 (or a multiple of 16) clock pulses over the SCK pin. The TLE 7241E will
simultaneously turn on the serial output SO and return the MISO return bits. When
receiving, valid data is latched on the rising edge of each SCK pulse. The serial output
data is available on the rising edge of SCK, and transitions on the falling edge of SCK.
See Figure 23 for SPI timing diagram.
The number of clock cycles occurring on the pin SCK while the CSB pin is asserted low
must be 16 or an integer multiple of 16, otherwise the SPI MOSI data will be ignored.
The fault registers are double buffered. The first buffer layer will latch a fault at the time
the fault is detected. This inner layer buffer is cleared when the fault condition is no
longer present and the fault bit has been communicated to the microprocessor by a
MISO response. The second layer buffer will latch the output of the inner layer buffer
whenever the CSB pin transitions from low to high. The output of this buffer layer is
transferred to the MISO shift register one SPI frame after the corresponding MOSI
command has been received from the microcontroller.
The MISO data word value of FFFF_H is never generated by the TLE 7241E, and will
indicate a Hi-Z state on the SO pin when an external pull-up resistor to V_DD is used. This
feature can be used to detect an open connection between the SO pin of the TLE 7241 E
and the microcontroller.
All undefined MOSI command words will be ignored by the TLE 7241E, and the MISO
response during the next SPI frame will be undefined (but not FFFF_H).
Note: The OL/SG fault bit is latched into the MISO register, and then updated within t_dly
(≤ 1.7 μs) after the rising edge of the CSB signal when the received MOSI word is
an General Configuration command.
Data Sheet
46
Rev. 1.1, 2009-01-19