PEB20542 Datasheet, PDF (40/300 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller with DMA

PEB 20542
PEF 20542
Pin Descriptions
Table 5
Test Interface Pins
Pin No.
Symbol In (I) Function
P-TQFP-
144-10
Out (O)
139 TRST I
JTAG Reset Pin (internal pull-up)
For proper device operation, a reset for the
boundary scan controller must be supplied to this
active low pin.
If the boundary scan of the SEROCCO-D is not
used, this pin can be connected to V_SS to keep it
in reset state.
5
TCK I
JTAG Test Clock (internal pull-up)
If the boundary scan of the SEROCCO-D is not
used, this pin may remain unconnected.
140 TDI
I
JTAG Test Data Input (internal pull-up)
If the boundary scan of the SEROCCO-D is not
used, this pin may remain unconnected.
4
TDO O
JTAG Test Data Output
62
TMS I
JTAG Test Mode Select (internal pull-up)
If the boundary scan of the SEROCCO-D is not
used, this pin may remain unconnected.
99
TEST1 I
100 TEST2 I
Test Input 1
When connected to V_DD3 the SEROCCO-D works
in a vendor specific test mode.
This pin must be connected to V_SS.
Test Input 2
When connected to V_DD3 the SEROCCO-D works
in a vendor specific test mode.
This pin must be connected to V_SS.
Data Sheet
40
2000-09-14