PEB20542 Datasheet, PDF (224/300 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller with DMA

PEB 20542
PEF 20542
Register Description (ISR2)
RDO
RFO
PCE
FERR
Receive Data Overflow Interrupt
(hdlc mode)
This bit is set to ’1’, if receive data of the current frame got lost because
of a SCC receive FIFO full condition. However the rest of the frame is
received and discarded as long as the receive FIFO remains full and is
stored as soon as FIFO space is available again. The receive status byte
(RSTA) of such a frame contains an ’RDO’ indication. In DMA operation
the ’RDO’ indication is also set in the receive byte count register RBCH.
Receive FIFO Overflow Interrupt
(all modes)
HDLC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and a complete frame
must be discarded. This interrupt can be used for statistical purposes,
indicating that the host was not able to service the SCC receive FIFO
quickly enough, e.g. due to high bus latency.
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and another received
character has been discarded. This interrupt can be used for statistical
purposes and might indicate that the host was not able to service the
SCC receive FIFO quickly enough, e.g. bus latencies are too high.
Protocol Error Interrupt
(hdlc mode)
This bit is valid in HDLC Automode only.
It is set to ’1’, if the receiver has detected a protocol error, i.e. one of the
following events occured:
• an S- or I-frame was received with wrong N(R) counter value;
• an S-frame containing an Information field was received.
Framing Error Interrupt
(async mode)
This bit is set to ’1’, if a character framing error is detected, i.e. a ’0’ was
sampled at a position where a stop bit ’1’ was expected due to the
selected character format.
Data Sheet
5-224
2000-09-14