XC886 Datasheet, PDF (39/119 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

XC886/888CLM
Functional Description
Table 11 ADC Register Overview (cont’d)
Addr Register Name
Bit
CA_H
ADC_CHCTR0
Reset: 00_H Bit Field
Channel Control Register 0
Type
CB_H
ADC_CHCTR1
Reset: 00_H Bit Field
Channel Control Register 1
Type
CC_H
ADC_CHCTR2
Reset: 00_H Bit Field
Channel Control Register 2
Type
CD_H
ADC_CHCTR3
Reset: 00_H Bit Field
Channel Control Register 3
Type
CE_H
ADC_CHCTR4
Reset: 00_H Bit Field
Channel Control Register 4
Type
CF_H
ADC_CHCTR5
Reset: 00_H Bit Field
Channel Control Register 5
Type
D2_H
ADC_CHCTR6
Reset: 00_H Bit Field
Channel Control Register 6
Type
D3_H
ADC_CHCTR7
Reset: 00_H Bit Field
Channel Control Register 7
Type
RMAP = 0, Page 2
CA_H
ADC_RESR0L
Result Register 0 Low
Reset: 00_H Bit Field
Type
CB_H
ADC_RESR0H
Reset: 00_H Bit Field
Result Register 0 High
Type
CC_H
ADC_RESR1L
Result Register 1 Low
Reset: 00_H Bit Field
Type
CD_H
ADC_RESR1H
Reset: 00_H Bit Field
Result Register 1 High
Type
CE_H
ADC_RESR2L
Result Register 2 Low
Reset: 00_H Bit Field
Type
CF_H
ADC_RESR2H
Reset: 00_H Bit Field
Result Register 2 High
Type
D2_H
ADC_RESR3L
Reset: 00_H Bit Field
Result Register 3 Low
Type
D3_H
ADC_RESR3H
Reset: 00_H Bit Field
Result Register 3 High
Type
RMAP = 0, Page 3
CA_H
ADC_RESRA0L
Reset: 00_H Bit Field
Result Register 0, View A Low
Type
CB_H
ADC_RESRA0H
Reset: 00_H Bit Field
Result Register 0, View A High
Type
CC_H
ADC_RESRA1L
Reset: 00_H Bit Field
Result Register 1, View A Low
Type
CD_H
ADC_RESRA1H
Reset: 00_H Bit Field
Result Register 1, View A High
Type
CE_H
ADC_RESRA2L
Reset: 00_H Bit Field
Result Register 2, View A Low
Type
CF_H
ADC_RESRA2H
Reset: 00_H Bit Field
Result Register 2, View A High
Type
D2_H
ADC_RESRA3L
Reset: 00_H Bit Field
Result Register 3, View A Low
Type
D3_H
ADC_RESRA3H
Reset: 00_H Bit Field
Result Register 3, View A High
Type
765432
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
0
LCC
0
r
rw
r
RESULT[1:0] 0
VF DRC
rh
r
rh
rh
RESULT[9:2]
rh
RESULT[1:0] 0
VF DRC
rh
r
rh
rh
RESULT[9:2]
rh
RESULT[1:0] 0
VF DRC
rh
r
rh
rh
RESULT[9:2]
rh
RESULT[1:0] 0
VF DRC
rh
r
rh
rh
RESULT[9:2]
rh
RESULT[2:0]
rh
RESULT[2:0]
rh
RESULT[2:0]
rh
RESULT[2:0]
rh
VF DRC
rh
rh
RESULT[10:3]
rh
VF DRC
rh
rh
RESULT[10:3]
rh
VF DRC
rh
rh
RESULT[10:3]
rh
VF DRC
rh
rh
RESULT[10:3]
rh
10
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
Data Sheet
Prelimary
35
V0.1, 2006-02