XC886 Datasheet, PDF (110/119 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

XC886/888CLM
4.3.3 Power-on Reset and PLL Timing
Electrical Parameters
Table 43
Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min. typ. max.
Pad operating voltage V_PAD CC 2.3 –
On-Chip Oscillator
start-up time
t_OSCST –
–
CC
–
V
500 ns
Flash initialization time t_FINIT CC –
RESET hold time¹⁾
t_RST SR –
160 –
500 –
µs
µs V_DDP rise time
(10% – 90%) ≤ 500µs
PLL lock-in in time
t_LOCK CC –
–
200 µs
PLL accumulated jitter D_P
–
–
tbd ns ²⁾
1) _{RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V).}
2) _{PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.}
Data Sheet
Prelimary
106
V0.1, 2006-02