TLE8242-2 Datasheet, PDF (36/78 Pages) Infineon Technologies AG – 8 Channel Fixed Frequency Constant Current Control With Current Profile Detection

TLE8242-2
5.9.1 SPI Signal Description
Functional Description and Electrical Characteristics
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified). Maximum capacitive load on the SO pin = 200 pF.
Pos. Parameter
5.9.1 Lead Time
5.9.2 Lag Time
Symbol
t₁
Limit Values
Min. Typ. Max.
140 –
–
t₂
50
–
–
5.9.3 Dead time
t₃
450 –
–
5.9.4
5.9.5
1/F_SCK Period of SCK
SCK to CSB set up time
t₄
100 –
–
t₅
10
–
–
5.9.6 SCK high time
t₆
40
–
–
5.9.7 SCK low time
t₇
40
–
–
5.9.8 CSB to SCK hold time
t₈
10
–
–
5.9.9 SI setup time
t₉
20
–
–
5.9.10 SI hold time
t₁₀
20
–
–
5.9.11 SO enable
t₁₁
–
–
110
5.9.12 SO valid time
t₁₂
–
–
80
5.9.13 SO disable time
t₁₃
–
–
110
5.9.14 Number of clock pulses while CS_B
low
32
–
32
5.9.15 SO rise time
T_{SO_RISE} –
–
50
5.9.16 SO fall time
T_{SO_FALL} –
–
50
5.9.17 Input pin capacitance. CS_B, SI, C_in
–
–
20
and SCK
5.9.18 SO pin capacitance
C_so
–
–
25
Unit Conditions
ns
CS_B falling (0.8V)
to SCK rising (0.8V)
ns
SCK falling (0.8V)
to CS_B rising
(0.8V)
ns
CS_B rise (2.0V) to
CS_B fall (2.0V)
ns
SCK rise to rise
ns
SCK falling (0.8V)
to CS_B fall (2.0V)
ns
SCK high time (rise
2.0V to fall 2.0V)
ns
SCK low time (fall
0.8V to rise 0.8V)
ns
CS_B rise (2.0V) to
SCK rise (0.8V)
ns
SI setup time to
SCK rise (0.8V)
ns
SI hold time after
SCK rise (2.0V)
ns
CS_B fall (2.0V) to
SO Bit0 valid
ns
SO data valid after
SCK rise (2.0V)
ns
SO tristate after
CS_B rise (2.0V)
cycles
ns
(20% to 80%)
ns
(80% to 20%)
pF
pF Tristate
Data Sheet
36
Rev. 1.0, 2010-02-09