TLE8242-2 Datasheet, PDF (19/78 Pages) Infineon Technologies AG – 8 Channel Fixed Frequency Constant Current Control With Current Profile Detection

TLE8242-2
Functional Description and Electrical Characteristics
norm al
turn off
tim e
OUTx
T1
PWM/32 CLK
PHASE_SYNC
gate turns off
on-tim e cut
sh o rt
T1
Program m ed delay =
8/32 PWM periods
Figure 8 Phase Synchronization Diagram
The TEST, SCI3, SCO2, SCO3, and AMUX pins are used during IC level test. These pins should be connected
directly to ground for normal device operation.
The FAULT pin is an open drain output pin. This pin will be pulled low by the device when an unmasked fault has
been detected. The fault masks are programmed via SPI message #1.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, T_j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
Parameter
Logic input low voltage
Logic input high voltage
Logic output low voltage
Logic output high voltage
Pull down digital input (SI, CLK,
SCK, PHASE_SYNC, ENABLE)
Pull up digital input (CS_B,
RESET_B)
Symbol
V_ILMAX
V_IHMIN
V_OLMAX
V_OHMIN
I_pd
Limit Values
Min. Typ. Max.
–
–
0.8
2.0
–
–
–
–
0.2
0.8*V_ –
–
SIGNAL
10
–
50
I_pu
-50 –
-10
5.2.7 Fault pin voltage
V_fault.low –
–
0.4
5.2.8 Fault pin current
I_fault,max 2.0
–
5.2.9
5.2.10
CLK high time (rise 2.0V to fall
t₁₄
2.0V)
CLK low time (fall 0.8V to rise 0.8V) t₁₅
8
–
–
8
–
–
Unit
V
V
V
V
µA
µA
V
mA
ns
ns
Conditions
I_L=200µA
I_L=-200µA
V_in=V_SIGNAL
V_in=0V (Current
drain from
V_SIGNAL)
Active state;
I_fault=2mA
Active state;
V_fault=0.4V
Data Sheet
19
Rev. 1.0, 2010-02-09