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TLE7237SL Datasheet, PDF (31/36 Pages) Infineon Technologies AG – SPI Driver for Enhanced Relay Control
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SPI Driver for Enhanced Relay Control
TLE7237SL
Serial Peripheral Interface (SPI)
9.6
Electrical Characteristics
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Input Characteristics (CS, SCLK, SI)
9.6.1 L level of pin
CS
SCLK
SI
9.6.2 H level of pin
CS
SCLK
SI
9.6.3 L-input pull-up current through CS
VCS(L)
VSCLK(L)
VSI(L)
VCS(H)
VSCLK(H)
VSI(H)
ICS(L)
9.6.4 H-input pull-up current through CS ICS(H)
9.6.5 L-input pull-down current through pin ISCLK(L)
SCLK
ISI(L)
SI
9.6.6 H-input pull-down current through pin ISCLK(H)
SCLK
ISI(H)
SI
Output Characteristics (SO)
0
–
0.5*VDD –
5
40
2.5
–
1.5
–
10
40
0.2*VDD V –
VDD
V–
90
µA VCS = 0 V
VDD = 5 V
–
µA 1)
VDD = 5 V
VCS = 0.5*VDD
–
µA 1)
VDD = 5 V
VSCLK = VSI = 0.2*VDD
µA 1)
80
VDD= 5 V
VSCLK = VSI = VDD
9.6.7 L level output voltage
9.6.8 H level output voltage
VSO(L)
0
– 0.4
V ISO = +2 mA
VSO(H)
VDD - –
VDD
0.4 V
ISO = -1.5 mA
9.6.9 Output tristate leakage current
Timings
ISO(OFF)
-10
– 10
µA VCS = VDD
9.6.10 Serial clock frequency
fSCLK
0
–5
9.6.11 Serial clock period
tSCLK(P)
200
–
–
9.6.12 Serial clock high time
tSCLK(H)
50
––
9.6.13 Serial clock low time
tSCLK(L)
50
––
9.6.14 Enable lead time (falling CS to rising tCS(lead) 250
–
–
SCLK)
9.6.15 Enable lag time (falling SCLK to rising tCS(lag)
250
–
–
CS )
MHz –
ns –
ns 1)
ns 1)
ns 1)
ns 1)
9.6.16 Transfer delay time (rising CS to
falling CS )
9.6.17 Data setup time (required time SI to
falling SCLK)
9.6.18 Data hold time (falling SCLK to SI)
tCS(td)
tSI(su)
tSI(h)
250 – –
20
––
20
––
ns 1)
ns 1)
ns 1)
Data Sheet
32
Rev. 1.0, 2010-02-18
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