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TLE6209R_07 Datasheet, PDF (3/30 Pages) Infineon Technologies AG – 7 A H-Bridge for DC-Motor Applications
TLE 6209 R
1.2.1
Pin Definitions and Functions
Pin No. Symbol Function
1, 10, GND
11, 20
Ground; internally connected to cooling tab (heat slug); to reduce
thermal resistance place cooling areas and thermal vias on PCB.
2,3
OUT1 Output 1; output of D-MOS half bridge 1; external connection
between pin 2 and pin 3 is necessary.
4,17 VS
Power supply; needs a blocking capacitor as close as possible to
GND; 47 µF electrolytic in parallel to 220 nF ceramic is
recommended; external connection between pin 4 and pin 17 is
necessary.
5
SCLK Serial clock input; clocks the shiftregister; SCLK has an internal
active pull down and requires CMOS logic levels
6
SDI
Serial data input; receives serial data from the control device;
serial data transmitted to SDI is an 8 bit control word with the Least
Significant Bit (LSB) being transferred first; the input has an active
pull down and requires CMOS logic levels; SDI will accept data on
the falling edge of SCLK-signal; see Table 1 for input data protocol.
7
SDO Serial-Data-Output; this tri-state output transfers diagnosis data to
the control device; the output will remain tri-stated unless the device
is selected by a low on Chip-Select-Not (CSN); SDO state changes
on the rising edge of SCLK; see Table 4 for diagnosis protocol.
8
CSN Chip-Select-Not input; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when SCLK is low; CSN has an
internal active pull up and requires CMOS logic levels.
9
INH
Inhibit input; has an internal pull down; device is switched in
standby condition by pulling the INH terminal low.
12
DIS
Disable input; has an internal pull up; the output stages are
switched in tristate condition by pulling the DIS terminal high.
13
DIR
Direction input; has an internal pull down; TTL/CMOS compatible
input.
14
PWM PWM input; has an internal pull down; TTL/CMOS compatible
input.
15
VCC
Logic supply voltage; needs a blocking capacitor as close as
possible to GND; 10 µF electrolytic in parallel to 220 nF ceramic is
recommended.
Data Sheet, Version 3.1
3
2007-08-01