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XC164CS-32F_06 Datasheet, PDF (29/81 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core | |||
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XC164-32
Derivatives
Functional Description
The XC164CS also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called âHardware Trapsâ.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector Trap Trap
Location1) Number Priority
Reset Functions:
â
⢠Hardware Reset
⢠Software Reset
⢠Watchdog Timer
Overflow
RESET
xxâ0000H 00H
III
RESET
xxâ0000H 00H
III
RESET
xxâ0000H 00H
III
Class A Hardware Traps:
⢠Non-Maskable Interrupt NMI
NMITRAP xxâ0008H 02H
II
⢠Stack Overflow
STKOF STOTRAP xxâ0010H 04H
II
⢠Stack Underflow
STKUF STUTRAP xxâ0018H 06H
II
⢠Software Break
SOFTBRK SBRKTRAP xxâ0020H 08H
II
Class B Hardware Traps:
⢠Undefined Opcode
⢠PMI Access Error
⢠Protected Instruction
Fault
UNDOPC BTRAP
PACER BTRAP
PRTFLT BTRAP
xxâ0028H 0AH
I
xxâ0028H 0AH
I
xxâ0028H 0AH
I
⢠Illegal Word Operand
Access
ILLOPA
BTRAP
xxâ0028H 0AH
I
Reserved
â
â
[2CH - 3CH] [0BH -
0FH]
Software Traps
â
â
Any
Any
⢠TRAP Instruction
[xxâ0000H - [00H -
xxâ01FCH] 7FH]
in steps of
4H
1) Register VECSEG defines the segment where the vector table is located to.
â
Current
CPU
Priority
Data Sheet
27
V1.1, 2006-08
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