XC164CS-32F_06 Datasheet, PDF (21/81 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164-32
Derivatives
Functional Description
RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC164CS Memory Map¹⁾
Address Area
Start Loc. End Loc. Area Size²⁾ Notes
Flash register space FF’F000_H
Reserved (Acc. trap) FE’0000_H
Reserved for EPSRAM F8’1800_H
Emul. Program
SRAM⁴⁾
F8’0000_H
FF’FFFF_H
FF’EFFF_H
FD’FFFF_H
F8’17FF_H
4 Kbytes
60 Kbytes
378 Kbytes
6 Kbytes
3)
–
–
2^nd way to PSRAM
Reserved for PSRAM
Program SRAM
Reserved for program
memory
E0’1800_H
E0’0000_H
C4’0000_H
F7’FFFF_H
E0’17FF_H
DF’FFFF_H
< 1.5 Mbytes Minus PSRAM
6 Kbytes
Maximum
< 2 Mbytes Minus Flash
Program Flash/ROM
Reserved
External memory area
C0’0000_H
BF’0000_H
40’0000_H
C3’FFFF_H
BF’FFFF_H
BE’FFFF_H
256 Kbytes
64 Kbytes
< 8 Mbytes
–
–
Minus reserved
segment
External IO area⁵⁾
20’0800_H 3F’FFFF_H < 2 Mbytes Minus TwinCAN
TwinCAN registers
20’0000_H 20’07FF_H 2 Kbytes
–
External memory area 01’0000_H 1F’FFFF_H < 2 Mbytes Minus segment 0
Data RAMs and SFRs 00’8000_H 00’FFFF_H 32 Kbytes Partly used
External memory area 00’0000_H 00’7FFF_H 32 Kbytes –
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) The Emulation PSRAM (EPSRAM) realizes a 2^nd access path to the PSRAM with a different timing.
Data Sheet
19
V1.1, 2006-08