TLE7235E Datasheet, PDF (29/37 Pages) Infineon Technologies AG – 8 Channel High-Side and Low-Side Relay Switch with Limp Home Mode

TLE7235E
Serial Peripheral Interface (SPI)
MI
MO
MCS
MCLK
time
SO device 3
SI device 3
SO device 2
SI device 2
Figure 11 Data Transfer in Daisy Chain Configuration
SO device 1
SI device 1
SPI_DasyChain2.emf
9.3
SPI Protocol
The control and diagnosis function of the TLE7235E is based on two register banks which are accessed via
following SPI protocol. The control register bank contains eight registers (with 4 bit each) addressed by a 3 bit
pointer. The diagnosis register bank contains four registers (with 4 bit each) addressed by a 2 bit pointer. An
additional indication bit is available to differentiate between standard diagnosis information and data read from a
register bank.
Control and Diagnosis Mode
CS¹⁾
7
6
5
4
3
2
1
0
Write Register Command
SI
1
ADDR
DATA
Read Register Command
SI
0
ADDR
x
x
0
RB
Read Standard Diagnosis
SI
0
x
x
x
x
x
1
x
Standard Diagnosis
S
TER
0
O
0
AWK
LH
D67
D45
D23
D01
Second Frame of Read Command
S
TER
0
O
1
ADDR (Diagnosis)
DATA
S
TER
1
O
ADDR (Control)
DATA
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame,
the output at SPI signal SO will contain the requested information. Any command can be executed in the
second frame.
Data Sheet
29
Rev. 1.0, 2008-10-30