TLE7235E Datasheet, PDF (12/37 Pages) Infineon Technologies AG – 8 Channel High-Side and Low-Side Relay Switch with Limp Home Mode

TLE7235E
Electrical Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Thermal Resistance¹⁾
Pos. Parameter
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Junction to Case, bottom
Junction to Case, top
Junction to Pin (6,7,18 or 19)
Junction to Ambient
(1s0p, min. footprint)
Junction to Ambient
(1s0p+300mm²Cu)
Junction to Ambient
(1s0p+600mm²Cu)
Junction to Ambient (2s2p)
Symbol
R_thJC,back
R_thJC,top
R_thJPin
R_thJA,min
Limit Values
Min. Typ. Max.
–
–
4
–
–
35
–
–
12
–
95
–
Unit
K/W
K/W
K/W
K/W
Conditions
2)
2)
2)
3)
R_thJA,300 –
50
–
K/W ⁴⁾
R_thJA,600 –
40
–
K/W ⁵⁾
R_thJA,2s2p –
31
–
K/W ⁶⁾
1) Not subject to production test
2) Specified R_thJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
T_a = 85 °C. Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
3) Specified R_thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 µm thickness.
T_a = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4) Specified R_thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm²
and 70 µm thickness. T_a = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
5) Specified R_thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm²
and 70 µm thickness. T_a = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
6) Specified R_thJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
T_a = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
Data Sheet
12
Rev. 1.0, 2008-10-30