1ED020I12FTA_16 Datasheet, PDF (29/31 Pages) Infineon Technologies AG – Single IGBT Driver IC

1ED020I12FTA
Single IGBT Driver IC
Application Notes
9
Application Notes
9.1
Reference Layout for Thermal Data
The PCB layout shown in Figure 9-1 represents the reference layout used for the thermal characterisation. Pins
11, 12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving
maximum power dissipation. The 1ED020I12FTA is conceived to dissipate most of the heat generated through
this pins.
Figure 9-1 Reference Layout for Thermal Data (Copper thickness 102 μm)
9.2
Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout.
• Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
• The same minimum distance between two adjacent high-side isolated parts of the PCB should be
maintained to increase the effective isolation and reduce parasitic coupling.
• In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be
kept as short as possible.
• Lowest trace length for VEE2 to GND2 decoupling could be achieved with capacitor closed to pins 2 and 4.
Data Sheet
29
Rev. 3.0
2016-04-05