PEB3265FV1.5 Datasheet, PDF (266/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
5.3
SLICOFI-2S Command Structure and Programming
This section describes only the SLICOFI-2S PEB 3264 command structure and
programming. Therefore, this section pertains only to the DuSLIC-S and DuSLIC-S2
chip sets.
5.3.1 SOP Command
The Status Operation (SOP) command provides access to the configuration and status
registers of the SLICOFI-2S. Common registers change the mode of the entire
SLICOFI-2S chip. All other registers are channel-specific. It is possible to access single
or multiple registers. Multiple register access is achieved by an automatic offset
increment. Write access to read-only registers is ignored and does not abort the
command sequence. Offsets may change in future versions of the SLICOFI-2S.
Attention: To ensure proper functionality, it is essential that all unused register
bits have to be filled with zeros.
5.3.1.1 SOP Register Overview
00_H
REVISION
Revision Number (read-only)
REV[7:0]
01_H
CHIPID 1
Chip Identification 1 (read-only)
for internal use only
02_H
CHIPID 2
Chip Identification 2 (read-only)
for internal use only
03_H
CHIPID 3
Chip Identification 3 (read-only)
for internal use only
04_H
FUSE1
Fuse Register 1
for internal use only
05_H
PCMC1
PCM Configuration Register 1
DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 SHIFT
PCMO[2:0]
Preliminary Data Sheet
266
DS3, 2003-07-11