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XC164GM_07 Datasheet, PDF (25/69 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core | |||
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XC164GM
Derivatives
Functional Description
Table 4
XC164GM Interrupt Nodes (contâd)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
Unassigned node
â
xxâ0040H
10H / 16D
Unassigned node
â
xxâ0044H
11H / 17D
Unassigned node
â
xxâ0048H
12H / 18D
Unassigned node
â
xxâ004CH
13H / 19D
Unassigned node
â
xxâ0050H
14H / 20D
Unassigned node
â
xxâ0054H
15H / 21D
Unassigned node
â
xxâ0058H
16H / 22D
Unassigned node
â
xxâ005CH
17H / 23D
Unassigned node
â
xxâ0078H
1EH / 30D
Unassigned node
â
xxâ007CH
1FH / 31D
Unassigned node
â
xxâ0080H
20H / 32D
Unassigned node
â
xxâ0084H
21H / 33D
Unassigned node
â
xxâ00FCH
3FH / 63D
Unassigned node
â
xxâ0100H
40H / 64D
Unassigned node
â
xxâ0104H
41H / 65D
Unassigned node
â
xxâ012CH
4BH / 75D
Unassigned node
â
xxâ0134H
4DH / 77D
Unassigned node
â
xxâ0138H
4EH / 78D
Unassigned node
â
xxâ013CH
4FH / 79D
Unassigned node
â
xxâ0140H
50H / 80D
Unassigned node
â
xxâ0160H
58H / 88D
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
23
V1.2, 2007-03
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