82C900 Datasheet, PDF (25/29 Pages) Infineon Technologies AG – Standalone TwinCAN Controller

82C900
Preliminary
Timings of the SSC
In the case that the SSC is used in slave mode without the RDY signal, the following
timings have to be respected:
Parameter
First activation of SLS
after end of reset
SLS active after SLS inactive
(to start a new communication cycle)
SLS active before SCLK active
in order to transfer the address byte
SLS inactive after SLS active
without transfer of data
Time after the address transfer
to the first data byte transfer
Time between two byte transfers
(SCLK active to SCLK active)
Time to SLS inactive after last byte
transfer
Min. Time
(access to
TwinCAN
registers)
1100
4
2
2
5 (write)
14 (read)
5 (write)
14 (read)
11 (write)
1 (read)
Min. Time
(access to
standalone
registers)
1100
4
2
2
5 (write)
11 (read)
5 (write)
11 (read)
6 (write)
1 (read)
Units
T_CAN
T_CAN
T_CAN
T_CAN
T_CAN
T_CAN
T_CAN
Note: The RDY signal can be used for a handshake to access to the device.
Furthermore, this signal indicates SSC error conditions (see baud rate error
detection). Accesses to the device during an SSC error condition can not be
correctly taken into account and might lead to errors.
Data Sheet
25
V 1.0D3, 2001-03