82C900 Datasheet, PDF (12/29 Pages) Infineon Technologies AG – Standalone TwinCAN Controller

82C900
Preliminary
Table 1
Symbol
CTRL3
P7
P6
P5
P4
P3
P2
P1
P0
OUT0 ²⁾
OUT1
MODE0 ³⁾
Pin Definitions and Functions (cont’d)
Pin
I/O ¹⁾ Function
Number
19
I/O Control 3
MODE0=0: Read or Read/Write Enable, RD or E
MODE1=0: Input used as read signal RD
MODE1=0: Read/write enable
MODE0=1: Master Receive Slave Transmit MRST
MODE1=0: Serial data output
MODE1=1: Serial data input
15
I/O Parallel Bus
14
MODE0=0: 8-bit Address/ Data Bus AD[7:0]
16
Address and data bus AD7..AD0 in 8-bit multiplexed
13
modes.
17
MODE0=1: 8-bit parallel I/O Port IO[7:0]
12
Programmable 8-bit general purpose I/O-port IO7..IO0.
18
11
6
O Output Line 0
The logic 0 level at this pin indicates an interrupt request
to the external host device if selected as interrupt output.
The interrupt line will be active if there is a new pending
interrupt request for interrupt node 0 (according to
register GLOBCTR).
If selected as clock output, the functionality is defined by
register CLKCTR.
23
O, Output Line 1
open The logic 0 level at this pin indicates an interrupt request
drain to the external host device.
The interrupt line will be active if there is a new pending
interrupt request for interrupt node 1 (according to
register GLOBCTR).
26
I/O, Interface Selection
open Pin MODE0 selects whether the on-chip SSC or an 8-bit
drain multiplexed bus are used to access the TwinCAN device.
MODE0=0: 8-bit multiplexed address/data bus
MODE0=1: on-chip SSC
After registering the initial state of MODE0 with the rising
edge of the reset signal, the respective pin can be used
as additional general purpose or special function I/O line
according register IOMODE4.
Data Sheet
12
V 1.0D3, 2001-03