English
Language : 

TLE7243SL Datasheet, PDF (23/28 Pages) Infineon Technologies AG – 8 Channel Protected Low-Side Relay Switch
◁
SPI Driver for Enhanced Relay Control
SPIDER - TLE7243SL
Serial Peripheral Interface (SPI)
8.4
SPI Characteristics
Note: Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Serial Peripheral Interface (SPI)
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 °C to +150 °C
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Input Characteristics (CS, SCLK, SI)
8.4.1 L level of pin
0
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
8.4.2 H level of pin
0.4*
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
VDD
8.4.3 L-input pull-up current through CS ICS(L)
3
17
8.4.4 H-input pull-up current through CS ICS(H)
3
15
8.4.5 L-input pull-down current through
3
12
pin
SCLK
SI
ISCLK(L)
ISI(L)
8.4.6 H-input pull-down current through
10
40
pin
SCLK
SI
ISCLK(H)
ISI(H)
Output Characteristics (SO)
0.2*
VDD
VDD
40
μA
VCS = 0 V
40
μA
1)
VCS = 0.4*VDD
80
μA
1)
VSCLK = 0.6 V
VSI = 0.6 V
80
μA
VSCLK = VDD
VSI = VDD
8.4.7
8.4.8
L level output voltage
H level output voltage
VSO(L)
VSO(H)
0
VDD -
0.4 V
0.6
V
VDD
ISO = -2 mA
ISO = 1.5 mA
8.4.9 Output tristate leakage current
Timings
ISO(OFF) -10
8.4.10
8.4.11
8.4.12
8.4.13
8.4.14
Serial clock frequency
Serial clock period
Serial clock high time
Serial clock low time
Enable lead time (falling CS to
rising SCLK)
fSCLK
tSCLK(P)
tSCLK(H)
tSCLK(L)
tCS(lead)
0
200
50
50
250
8.4.15 Enable lag time (falling SCLK to tCS(lag) 250
rising CS)
8.4.16 Transfer delay time (rising CS to tCS(td)
250
falling CS)
8.4.17 Data setup time (required time SI to tSI(su)
20
falling SCLK)
10
μA
VCS = VDD
5
MHz 1)
ns
1)
ns
1)
ns
1)
ns
1)
ns
1)
ns
1)2)
ns
1)
Datasheet
23
Rev. 1.0, 2009-09-30
 ▷