TLE7243SL Datasheet, PDF (20/28 Pages) Infineon Technologies AG – 8 Channel Protected Low-Side Relay Switch

SPI Driver for Enhanced Relay Control
SPIDER - TLE7243SL
Serial Peripheral Interface (SPI)
CS Low to High transition:
Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly
a multiple (1, 2, 3, …) of eight SCLK signals have been detected, while the minimum valid length is of course 16
clocks for the 16 register bits of SPIDER - TLE7243SL.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. Please refer to Section 8.3 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 8.3
for further information.
8.2
Daisy Chain Capability
The SPI of SPIDER - TLE7243SL provides daisy chain capability. In this configuration several devices are
activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device
(see Figure 10), which builds a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the
SCLK line of each device in the chain.
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCS
MCLK
SPI_DasyChain.emf
Figure 10 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 16 SCLK cycles, the data transfer for one SPIDER - TLE7243SL has been
finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In
daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using multiple
devices in daisy chain, the number of bits must be correspond with the number of register bits. Figure 11 is
showing a example with 3 SPI devices, where #1 and #3 are 16 bit SPI and #2 has a 8 bit SPI. To get a successful
transmission, there have to be 2* 16 bit + 1* 8bit shifted through the devices. After that, the MCS line must go high.
Datasheet
20
Rev. 1.0, 2009-09-30