TLE8201R Datasheet, PDF (21/45 Pages) Infineon Technologies AG – Door Module Power IC

TLE 8201R
4.3.4.1 Error-Flag
In addition to the 16 bits transferred from the TLE 7201R to the SPI master, an additional
Error Flag (EF) is transmitted at the DO pin. The EF status is shown on the DO pin after
CSN H->L, before the first rising edge at CLK, as shown in Figure 6.
The Error flag is set to H if any of the Status Registers contains an error message (i.e.
EF = EF_00 or EF_01 or EF_10 or EF_11)
.
CSN
CLK
DO Z
EF
bit15
bit14
bit13
bit12
CSN
CLK
DO Z
EF
Z
Figure 6
Error Flag transmission on DO during standard SPI transmission
(top), or without additional SPI transmission, CLK low (bottom)
4.3.5 Electrical Characteristics
Electrical Characteristics - SPI-timing
8 V < V_S < 20 V; 4.75 V < V_CC < 5.25 V; INH = High; all outputs open;
-40 °C < T_j < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values Unit
min. typ. max.
4.3.1 CSN lead time
t_lead
4.3.2 CSN lag time
t_lag
4.3.3 Fall time for CSN, CLK, DI, t_f
DO
100 –
100 –
––
– ns
– ns
25 ns
4.3.4 Rise time for CSN, CLK, t_r
DI, DO
– – 25 ns
Conditions
1¹⁾
2¹⁾
3¹⁾
4¹⁾
Data Sheet Rev. 2.0
21
2006-06-07