TDA5201 Datasheet, PDF (20/43 Pages) Infineon Technologies AG – ASK Single Conversion Receiver

TDA 5201
Functional Description
3.4.7 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator tolerance values. Both inputs are accessible. The output delivers a digital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin 20 its generated by RC-term or peak detector depending on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4.8 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The out-
put can be used as an indicator for the signal strength and also as a reference
for the data slicer. The maximum output current is 500µA.
3.4.9 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States
PDWN
Open or tied to ground
Tied to Vs
Operating State
Powerdown Mode
Receiver On
Wireless Components
3 - 12
Specification, July 2004