TDA5201 Datasheet, PDF (18/43 Pages) Infineon Technologies AG – ASK Single Conversion Receiver

TDA 5201
Functional Description
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-
tage gain of approximately 21dB by utilising either high- or low-side injection of
the local oscillator signal. In case the mixer is interfaced only single-ended, the
unused mixer input has to be tied to ground via a capacitor. The mixer is fol-
lowed by a low pass filter with a corner frequency of 20MHz in order to suppress
RF signals to appear at the IF output (IFO pin). The IF output is internally con-
sisting of an emitter follower that has a source impedance of approximately
330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter
without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO
was designed to guarantee over production spread and the specified tempera-
ture range a receive frequency range between 310 and 350MHz depending on
whether high- or low-side injection of the local oscillator is used. The oscillator
signal is fed both to the synthesiser divider chain and to a divider that is dividing
Wireless Components
3 - 10
Specification, July 2004