TDA5200_10 Datasheet, PDF (20/39 Pages) Infineon Technologies AG – ASK Single Conversion Receiver

TDA 5200
ASK Single Conversion Receiver
Functional Description
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilization of quartzes both in the 6 MHz and 13 MHz range as the
overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16) pin according to the
following table.
Table 3 CSEL Pin Operating States
CSEL
Open
Shorted to ground
Crystal Frequency
6.xx MHz
13.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Chapter 4.3, the quartz
frequency calculation is explained in Chapter 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a
bandpass-characteristic centered around 10.7 MHz. It has an input impedance of 330 Ω to allow for easy
interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI)
generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in
Figure 6. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to
turn down the LNA gain by approximately 17 dB in case the input signal strength is too strong as described in
Chapter 3.4.1 and Chapter 4.1.
3.4.6 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 kΩ on-
chip resistors. Along with two external capacitors a 2^nd order Sallen-Key low pass filter is formed. The selection of
the capacitor values is described in Chapter 4.2.
3.4.7 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of
approximately 120 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the
local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like
levels) for the detector. The self-adjusting threshold on pin 20 is generated by RC-term or peak detector
depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in
more detail in Chapter 4.5.
3.4.8 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An
external RC network is necessary. The output can be used as an indicator for the signal strength and also as a
reference for the data slicer. The maximum output current is 500 µA.
3.4.9 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode
is available to switch off all sub-circuits which is controlled by the PWDN pin (Pin 27) as shown in the following
table. The supply current drawn in this case is typically 50 nA.
Data Sheet
20
Revision 3.0, 2010-12-28