TDA5200_10 Datasheet, PDF (19/39 Pages) Infineon Technologies AG – ASK Single Conversion Receiver

3.4
Functional Blocks
TDA 5200
ASK Single Conversion Receiver
Functional Description
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 dB to 20 dB. The gain figure is determined by
the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer
Inputs MI and MIX (Pin 8 and Pin 9). The noise figure of the LNA is approximately 3.2 dB, the current consumption
is 500 µA. The gain can be reduced by approximately 18 dB. The switching point of this AGC action can be
determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared
internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is
higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated
by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output
generated from the internal bandgap voltage and the THRES pin as described in Chapter 4.1. The time constant
of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operating case and interference scenario
to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described
in Chapter 4.1.
3.4.2 Mixer
The Double Balanced Mixer down-converts the input frequency (RF) in the range of 433-435 MHz / 868-870 MHz
to the intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 21 dB. A low pass filter with a
corner frequency of 20 MHz is built on chip in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 Ω
to facilitate interfacing the pin directly to a standard 10.7 MHz ceramic filter without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with
charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor
diodes. It’s nominal centre frequency is 840 MHz. No additional components are necessary.
Local oscillator high side injection has to be used for receive frequencies below approximately 420 MHz or
840 MHz, low side injection for receive frequencies above approximately 420 MHz or 840 MHz - see also
Chapter 4.4. Therefore low-side injection of the local oscillator has to be used for operation both in the 868 MHz
and the 434 MHz ISM bands.
The oscillator signal is fed both to the synthesizer divider chain and to the down-converting mixer. In case of
operation in the 433-435 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled by
the selection pin FSEL (Pin 11) as described in the following table. The overall division ratio of the divider chain
can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below).
The loop filter is also realized fully on-chip.
Table 2 FSEL Pin Operating States
FSEL
Open
Shorted to ground
RF Frequency
433-435 MHz
868-870 MHz
Data Sheet
19
Revision 3.0, 2010-12-28