TDA5200 Datasheet, PDF (18/43 Pages) Infineon Technologies AG – ASK Single Conversion Receiver

TDA 5200
Functional Description
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 3.2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 433-435MHz/868-870MHz to the intermediate frequency (IF) at
10.7MHz with a voltage gain of approximately 21dB. A low pass filter with a cor-
ner frequency of 20MHz is built on chip in order to suppress RF signals to
appear at the IF output ( IFO pin). The IF output is internally consisting of an
emitter follower that has a source impedance of approximately 330 Ω=to facili-
tate interfacing the pin directly to a standard 10.7MHz ceramic filter without
additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. It’s nominal centre frequency is 852MHz. No additional components are
necessary. The oscillator signal is fed both to the synthesiser divider chain and
to the downconverting mixer. In case of operation in the 433 - 435 MHz range,
the signal is divided by two before it is fed to the mixer. This is controlled by the
selection pin FSEL (Pin 11) as described in the following table. The overall divi-
Wireless Components
3 - 10
Specification, March 2000