TLE6361G_05 Datasheet, PDF (17/57 Pages) Infineon Technologies AG – Multi-Voltage Processor Power Supply

TLE 6361 G
this point, thereby releasing the DO bus circuit for other uses. For details of the SPI
timing please refer to figures 10 to 13.
The SPI will be reset to default values given in the following table “write bit meaning” if
the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).
The reset will be active as long as the power on reset is present so during the reset delay
time at power up no SPI commands are acceptable.
The register content of the SPI - including watchdog timings and reset delay timings - is
maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not
decrease below 3.3V).
2.12.1 Write mode
The following tables show the bit assignment to the different control functions, how to
change settings with the right bit combination and also the default status at power up.
2.12.2 Write mode bit assignment
BIT
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D 15
Name
Default
WD_OF NOT
T1-
T2-
T6-
T4-
T5-
T6-
F1 assigned control control control control control control
sleep
W D_OF
F2
reset 1
reset 2
WD 1
WD 2
W D_OF
F3
W D-Trig
1
X
0
0
0
0
0
0
1
1
0
0
0
0
1
0
Figure 8 Write Bit assignment
Write Bit meaning
Function
Not assigned
Tracker 1 to 6 - control:
turn on/off the individual trackers
Power down:
send device to sleep
Bit
Combination Default
D1
X
X
D2
0: OFF
0
D3
1: ON
D4
D5
D6
D7
D8
0: SLEEP
1
1: NORMAL
Data Sheet, Rev. 2.0
17
2005-03-01